Program Committee
- Boma Anantasatya Adhi, Department of Electrical Engineering. Faculty of Engineering, Universitas Indonesia
- Giovanni Agosta, Politecnico di Milano
- Jason Bakos, University of South Carolina
- Davide Bertozzi, University of Manchester
- Xing Cai, Simula Research Laboratory
- Teresa Cervero, Barcelona Supercomputing Center
- Alex Delis, University of Athens
- Manuel F. Dolz, Universitat Jaume I
- Ryusuke Egawa, Tokyo Denki University
- Jesus Escudero-Sahuquillo, University of Castilla-La Mancha
- Jorge G. Barbosa, University of Porto
- Pedro Javier Garcia, Universidad de Castilla-La Mancha
- Vladimir Getov, University of Westminster
- Toshihiro Hanawa, Information Technology Center, The University of Tokyo
- Tanja Harbaum, ITIV, Karlsruhe Institute of Technology
- Christoph Kessler, Linköping University
- Benjamin Klenk, NVIDIA
- Ryohei Kobayashi, Institute of Science Tokyo
- Kazuhiko Komatsu, Tohoku University
- Heiner Litz, Stanford University
- Hatem Ltaief, King Abdullah University of Science and Technology
- George Michelogiannakis, LBNL
- Esteban Mocskos, UBA
- Mattias O'Nils, Mid Sweden University
- Francesca Palumbo, University of Cagliari
- Dhabaleswar Panda, The Ohio State University
- Marcus Paradies, LMU Munich
- Antonio J. Peña, Barcelona Supercomputing Center (BSC)
- Oscar Plata, University of Malaga
- Dirk Pleiter, University of Groningen / KTH Royal Institute of Technology
- Christian Plessl, Paderborn University
- Rohit Prasad, CEA
- Carlos Reaño, Universitat de València
- Julio Sahuquillo, Universitat Politècnica de València
- Kazem Shekofteh, Heidelberg University
- Shinji Sumimoto, The University of Tokyo
- Keita Teranishi, Oak Ridge National Laboratory
- Christian Terboven, RWTH Aachen University
- Samuel Thibault, LaBRI, Université Bordeaux 1, France
- Antonino Tumeo, Pacific Northwest National Laboratory
- Tomohiro Ueno, RIKEN
- Yoshiki Yamaguchi, University of Tsukuba
- Li Zhang, TU Darmstadt
Focus
- Architectures for instruction-level and thread-level parallelism
- Manycores, multicores, accelerators, domain-specific and special-purpose architectures, reconfigurable architectures
- Cloud and HPC storage architectures and systems
- Memory technologies and hierarchies
- Exascale system designs; data center and warehouse-scale architectures
- Novel big data architectures
- Parallel I/O and storage systems
- Power-efficient and green computing systems
- Resilience, security, and dependable architectures
- Software architectures spanning IoT/Edge, Fog, Cloud, 5G and HPC computing
- Processing in Memory and Near-Memory Processing
- Interconnect/memory architectures
- Post Moore era systems: neuromorphic, quantum, hybrid, ...
